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| GPS Down Converter IC CXA3355TQ Description The CXA3355TQ is an IC developed as a GPS RF down converter. This IC realizes a reduction in the number of external parts by integrating LNA, image rejection mixer, IF filter and PLL/VCO parts, such as inductor and variable capacitors. (Applications: GPS RF down converter IC) Features Includes all functions required for the GPS down converter Low voltage operation: VCC = 1.6 to 2.0V Low current consumption (active mode): 11mA (Typ. at VCC = 1.8V, IF 1MHz) Low current consumption (power save mode) < 1A Total gain 100dB Total NF 4.0dB On-chip VCO and PLL Selectable TCXO frequency On-chip LNA (NF = 2.0dB) Image rejection mixer On-chip IF filter, and an external filter can be connected as an option for further band narrowing. 1-bit IF output Package 48-pin TQFP (Plastic) Structure SiGe BiCMOS monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E05328 CXA3355TQ Absolute Maximum Ratings (Ta = 25C) Supply voltage VCC1 VCC2 Operating temperature Storage temperature Topr Tstg -0.2 to +2.5 -0.2 to +3.6 -40 to +85 -65 to +150 V V C C Recommended Operating Conditions Supply voltage VCC1 VCC2 1.6 to 2.0 1.6 to 3.3 V V -2- CXA3355TQ Block Diagram and Pin Configuration VCC1 (LNA) VCC1 (LNA) GND (LNA) 26 36 GND (RF) 37 35 34 33 32 31 30 29 28 27 25 24 GND (LNA) RF_AMP VCC1 (RF) 38 VCC1 (RF) 39 TESTINP 40 4fo [fo] TESTINN 41 IF_AMP1 TESTOUTP 42 TESTOUTN 43 VCC1 (IF) 44 GND (IF) 45 NC 46 R_EXT1 47 ENABLE 48 1 BIAS 2 3 4 IF Filter Mixer Mixer LNA 1540fo = 1575.42MHz 23 NC 22 NC 1536fo [1539fo] 21 VCO_I 90 20 C_VCO IF_AMP1 PLL DMPS MC SC PFD CP 18 LPF 17 VCC1 (PLL) 16 GND (PLL) 15 TCXO A/D Converter 14 CLK_OUT CTL 13 LT 5 6 7 8 9 10 11 12 19 GND IF Phase Shifter RC x2 IF_AMP2 NC NC NC GND NC C_EXT DATA_OUT R_EXT2 VCC2 (IF) GND (IF) DATA -3- CLK GND (LNA) LNA_OUT GND (RF) RF_INN RF_INP LNA_IN GND GND GND CXA3355TQ Pin Description Standard pin voltage [V] DC AC VCC1 (IF) Pin No. Symbol Equivalent circuit Description 1 R_EXT2 1.16 -- 1 1k GND (IF) External resistor connection. (bias) 2 3 4 5 6 NC NC NC GND NC -- -- -- 0 -- -- -- -- -- -- VCC1 (IF) Normally leave open. Normally leave open. Normally leave open. GND. Normally leave open. 7 C_EXT 1.2 -- 7 Capacitor connection for canceling the offset. GND (IF) VCC2 (IF) 8 DATA_OUT -- 1.8 Vp-p 8 DATA (IF) output. GND (IF) 9 10 VCC2 (IF) GND (IF) 1.8 0 -- -- IF block VCC. IF block GND. -4- CXA3355TQ Pin No. Symbol Standard pin voltage [V] DC AC -- Equivalent circuit Description 11 DATA -- VCC1 (PLL) Serial data input. 11 12 CLK -- -- 12 13 Serial data clock input. 13 LT -- -- GND (PLL) Latch signal input. VCC2 (IF) 14 CLK_OUT 1.2 -- 14 TCXO clock output. Leave open when not using the TCXO clock. GND (IF) VCC1 (PLL) 15 TCXO -- -- 15 Reference frequency input. GND (PLL) 16 17 GND (PLL) VCC1 (PLL) 0 1.8 -- -- VCC1 (PLL) PLL block GND. PLL block VCC. 18 LPF -- -- 18 PLL loop filter connection. GND (PLL) 19 GND 0 -- GND. -5- CXA3355TQ Pin No. Symbol Standard pin voltage [V] DC AC Equivalent circuit Description VCC1 (RF) 20 C_VCO -- -- 20 1k Capacitor connection for decoupling the VCO bias circuit. GND (RF) VCC1 (RF) 21 VCO_I -- -- 21 Capacitor connection for decoupling the VCO bias circuit. GND (RF) 22 23 24 25 26 NC NC GND (LNA) GND (LNA) GND (LNA) -- -- 0 0 0 -- -- -- -- -- VCC1 (LNA) Normally leave open. Normally leave open. LNA block GND. LNA block GND. LNA block GND. 27 LNA_IN 0.7 -- 30 LNA input. 27 30 LNA_OUT 1.8 -- GND (LNA) LNA output. 28 29 31 32 33 GND GND VCC1 (LNA) VCC1 (LNA) GND 0 0 1.8 1.8 0 -- -- -- -- -- GND. GND. LNA block VCC. LNA block VCC. GND. -6- CXA3355TQ Pin No. Symbol Standard pin voltage [V] DC AC Equivalent circuit Description VCC1 (RF) 34 RF_INN -- -- RF amplifier input. 34 35 35 RF_INP -- -- GND (RF) 36 37 38 39 GND (RF) GND (RF) VCC1 (RF) VCC1 (RF) 0 0 1.8 1.8 -- -- -- -- VCC1 (IF) RF block GND. RF block GND. RF block VCC. RF block VCC. 40 TESTINP 1.3 -- IF signal input when using an external filter. 40 41 41 TESTINN 1.3 -- GND (IF) IF signal input when using an external filter. VCC1 (IF) 42 TESTOUTP 0.5 -- 42 43 IF signal output when using an external filter. 43 TESTOUTN 0.5 -- GND (IF) IF signal output when using an external filter. 44 45 46 VCC1 (IF) GND (IF) NC 1.8 0 -- -- -- -- IF block VCC. IF block GND. Normally leave open. -7- CXA3355TQ Pin No. Symbol Standard pin voltage [V] DC AC Equivalent circuit Description VCC1 (IF) 47 R_EXT1 0.5 -- External resistor connection. (bias) 47 GND (IF) VCC1 (IF) 48 ENABLE -- -- 48 ENABLE signal input. High (V_IH: 1.2V min.): Active mode Low (V_IL: 0.2V max.): Power save mode GND (IF) -8- CXA3355TQ Electrical Characteristics DC Characteristics (VCC1 = VCC2 = 1.8V, Ta = 25C) Item Supply current 1 Supply current 2 Symbol ICC1 ICC2 fo mode Power save mode Conditions Min. 7 -- Typ. 11 0.1 Max. 15 1 Unit mA A Note) fo mode uses the following power-on reset conditions. fo mode: TCXO = 18.414MHz, fLO = 1574.397MHz, IF = 1.023MHz AC Characteristics (VCC1 = VCC2 = 1.8V, Ta = 25C) Item Total voltage gain Image rejection ratio LPF1 (fo mode) LPF2 (fo mode) LPF3 (fo mode) C/N 100K Symbol G IMRR LPF1 LPF2 LPF3 C/N Conditions Excluding the A/D converter Frequency = 1.023MHz @150kHz Normalized at 1.023MHz output level @2.046kHz Normalized at 1.023MHz output level @6MHz Normalized at 1.023MHz output level IF = fo, TCXO = 18.414MHz Min. 85 -- -5 -13 -- -- Typ. 100 -40 -- -- -- -70 Max. -- -20 4 2 -13 -55 Unit dB dBc dB dB dB dBc/Hz Note) fo mode uses the following power-on reset conditions. fo mode: TCXO = 18.414MHz, fLO = 1574.397MHz, IF = 1.023MHz -9- CXA3355TQ Design Reference Value of Operating Conditions IF Output (DATA_OUT) (VCC1 = VCC2 = 1.8V, Ta = 25C) Item DATA_OUT rise time DATA_OUT fall time Symbol DTr DTf Conditions Pin 8 (DATA_OUT), 10 to 90%, Load = 1M//13pF Pin 8 (DATA_OUT), 10 to 90%, Load = 1M//13pF Min. -- -- Typ. 6 4 Max. -- -- Unit ns ns ENABLE (VCC1 = 1.8 0.2V, VCC1 VCC2 3.3V, Ta = 25C) Item Input voltage High level Input voltage Low level Symbol EVIH EVIL Conditions Pin 48 (ENABLE), input voltage High level threshold voltage Pin 48 (ENABLE), input voltage Low level threshold voltage Min. 1.2 -0.1 Typ. -- -- Max. VCC2 + 0.2 0.2 Unit V V Power-on Reset (VCC1 = 1.8 0.2V, VCC1 VCC2 3.3V, Ta = 25C) Item Symbol Conditions ENABLE and power supply (VCC1, VCC2) rise time for the power-on reset function to operate. Allowable rise time MTr Note) Use an ENABLE and power supply (VCC1, VCC2) rise time of 100ms or less. -- -- 100 ms Min. Typ. Max. Unit TCXO (VCC1 = VCC2 = 1.8V, Ta = 25C) Item Input level CLK_OUT rise time CLK_OUT fall time Symbol Vtcxo CTr CTf Conditions Pin 15 (TCXO) Pin 14 (CLK_OUT), 10 to 90%, Load = 1M//13pF Pin 14 (CLK_OUT), 10 to 90%, Load = 1M//13pF Min. 0.2 -- -- Typ. 0.6 6 4 Max. 1.2 -- -- Unit Vp-p ns ns - 10 - CXA3355TQ Threshold Voltage (VCC1 = 1.8 0.2V, VCC1 VCC2 3.3V, Ta = 25C) Item Logic input voltage High level Logic input voltage Low level Logic output voltage High level Logic output voltage Low level Symbol VIH VIL VOH VOL Conditions Logic input pins = 11 (DATA), 12 (CLK), 13 (LT) Logic input pins = 11 (DATA), 12 (CLK), 13 (LT) Logic output pins = 8 (DATA_OUT), 14 (CLK_OUT) Logic output pins = 8 (DATA_OUT), 14 (CLK_OUT) Min. VCC2 - 0.2 -0.1 VCC2 - 0.2 0 Typ. -- -- -- -- Max. VCC2 + 0.2 0.2 VCC2 0.2 Unit V V V V - 11 - CXA3355TQ Electrical Characteristics Measurement Circuit RF_IN 3.3p 10n 3.3p 12p 36 GND (RF) LNA_OUT VCC1 (LNA) 100p 1p 3p 3.9n LNA_IN 50 matching condition 4.7p 3.9n 6p 35 RF_INP 34 RF_INN 33 GND 32 VCC1 (LNA) 31 VCC1 (LNA) 30 LNA_OUT 29 GND 28 GND 27 LNA_IN 26 GND (LNA) 25 GND (LNA) 10p VCC1 (RF) 37 GND (RF) GND (LNA) 24 38 VCC1 (RF) NC 23 39 VCC1 (RF) NC 22 0.1 40 TESTINP TESTIN Buffer 41 TESTINN VCO_I 21 0.1 C_VCO 20 42 TESTOUTP TESTOUT Buffer VCC1 (IF) 1n 45 GND (IF) 43 TESTOUTN GND 19 24k 100p LPF 18 8p VCC1 (PLL) 17 VCC1 (PLL) 10p GND (PLL) 16 10n TCXO input level: 0.2 to 1.2Vp-p VCC1 (PLL) 44 VCC1 (IF) 46 NC 33k 47 R_EXT1 VCC2 (IF) TCXO 15 CLK_OUT 14 CLK_OUT DATA_OUT 48 ENABLE R_EXT2 C_EXT LT 13 VCC2 (IF) GND (IF) DATA GND NC NC NC NC 1 39k 2 3 4 5 6 18n 7 8 9 10 11 12 ENABLE pin VCC2 (IF): Active mode GND: Power save mode DATA_OUT 1n VCC2 (IF) Bus Control Note) 1. The RF block bypass capacitors should have excellent high frequency characteristics. 2. Use parts with a tolerance of 1% for the following resistor elements. Other parts should have a tolerance of 5%. * Pin 1 (R_EXT2) * Pin 18 (LPF) * Pin 47 (R_EXT1) - 12 - CLK CXA3355TQ Initial Settings The CXA3355TQ is initialized by setting the ENABLE signal (Pin 48) from Low level to High level. The timing, etc. should satisfy the conditions below. In addition, the TCXO frequency and IF frequency combinations in the table below can be obtained by setting Pin 11 (DATA), Pin 12 (CLK) and Pin13 (LT) as shown in the table and then performing initialization. This eliminates the need for serial data setting. Pin 11 (DATA) GND VCC2 VCC2 Pin 12 (CLK) GND GND VCC2 Pin 13 (LT) GND GND GND TCXO frequency [MHz] Reserved 18.414 13 IF frequency [MHz] Reserved 1.023 0.976 1. During Power-on Power supply, ENABLE VCC 0.9 x VCC 0.1 x VCC GND 100ms or less The CXA3355TQ is initialized by simultaneously rising the power supplies and the ENABLE signal (Pin 48) during power-on. The power supply and ENABLE (Pin 48) rise time should be 100ms or less. In addition, the power supply (VCC1, VCC2) should rise simultaneously. 2. Initialization After Power-on Power supply VCC GND ENABLE VCC 0.5 x VCC GND 10ms or more After power-on, the CXA3355TQ is initialized by setting the ENBLE signal (Pin 48) to Low level for 10ms or more and then setting it to High level. - 13 - CXA3355TQ Serial Data Settings The CXA3355TQ can make the PLL counter settings, perform TCXO_CLK output, select the internal IF Filter, and use the test I/O circuit according to the serial data settings (3-wire bus control). The transfer bit length is 18 bits, and there are four addresses. The address is set by the A1 and A0 bits. The timing, etc. should satisfy the conditions below. Serial Data Format (MSB) A1 0 0 1 1 A0 0 1 0 1 D15 D14 D13 MC8 SC2 TI0 MC8 D12 MC7 SC1 TO2 MC7 D11 MC6 SC0 TO1 MC6 D10 MC5 RC8 TO0 MC5 D9 MC4 RC7 0 MC4 D8 MC3 RC6 0 MC3 D7 MC2 RC5 0 MC2 D6 MC1 RC4 0 MC1 D5 MC0 RC3 0 MC0 D4 0 RC2 0 0 D3 0 RC1 0 0 D2 0 RC0 0 0 D1 CLK 0 FIL CLK (LSB) D0 0 TCL 0 0 MC10 MC9 SC4 TI2 SC3 TI1 MC10 MC9 MC (0 to 10): Main counter frequency division value setting SC (0 to 4): Swallow counter frequency division value setting RC (0 to 8): Reference counter frequency division value setting CLK: TCXO CLK output (0: Not output, 1: Output) FIL: Internal filter selection (0: fo mode LPF, 1: Reserved) TCL: IF block test I/O control (0: When not using the test I/O circuit, 1: When using the test I/O circuit) TI (0 to 2): IF block test input location setting TO (0 to 2): IF block test output location setting 0: Logic input voltage Low level 1: Logic input voltage High level 18-bit Data Format Invalid data D0 DATA D1 D2 D3 D4 D5 D6 Each data D7 D8 D9 D10 D11 D12 D13 D14 D15 Address data Invalid data A0 A1 CLK LT Time Input data to all four addresses. Latch Serial Data Interface Bus Timing (3-wire Bus Control) tSD DATA tHD CLK tLOW tHIGH tSD = Data setup time tHD = Data hold time tLOW = Low period of CLK tHIGH = High period of CLK tSL = LT setup time tWHLT = High pulse width (LT) tHL tWHLT LT tWHLT 100ns tSD, tHD, tLOW, tHIGH, tHL, tWHLT 50ns - 14 - CXA3355TQ Description of Functions Test Circuit The CXA3355TQ has a test circuit for test signal I/O. The test circuit is connected between each IF block, and test I/O control can be performed by the serial data settings. The test circuit location, configuration and the serial data settings are as follows. To each IF block 37 RF_AMP 36 35 34 33 1540fo = 1575.42MHz 38 39 40 41 42 43 Test output control 43 44 45 "2" Actual operation is differential, but only one side is shown. 46 The inter-circuit connections are cut off during test input selection and test output selection. 47 48 1 BIAS 2 3 4 5 6 7 8 IF_AMP2 IF Filter "3" "4" A/D Converter IF Phase Shifter 42 "1I": Ich mixer output (Ich IF AMP1 output) "1Q": Qch mixer output (Qch IF AMP1 input) "2": Adder input (IF filter input) "3": IF filter input (IF AMP2 input) "4": IF AMP2 output (A/D converter input) Mixer Mixer Test input control 40 41 "1Q" IF_AMP1 "1I" 90 IF_AMP1 Local From each IF block Test Circuit Location and Configuration Serial Data Settings for Test Input Selection TI2 0 0 0 0 1 1 1 1 TI1 0 0 1 1 0 0 1 1 TI0 0 1 0 1 0 1 0 1 Test input Normal operation Ich IF AMP1 input Qch IF AMP1 input Not used. Not used. IF filter input IF AMP2 input A/D converter input Serial Data Settings for Test Output Selection TO2 0 0 0 0 1 1 1 1 TO1 0 0 1 1 0 0 1 1 TO0 0 1 0 1 0 1 0 1 Test output Normal operation Ich mixer output Qch mixer output Not used. Not used. Adder output IF filter output IF AMP2 output 0: Logic input level Low level 1: Logic input level High level Note) Set the TCL register to "1" when using or to "0" when not using the test input circuit or the test output circuit. (See page 14.) - 15 - CXA3355TQ Description of Operation Overview of Operation This IC down-converts the GPS (Global Positioning System) frequency of 1.57542GHz to fo (fo: 1.023MHz). The internal configuration is divided into the analog block, consisting of the amplifier, mixer and filters, and the digital block (including the comparator block and the control block), which forms PLL. The analog block converts the frequency and amplifies the signal with the amplifier and the mixer, and eliminates undesired components with the filters. The digital block can switch the PLL frequency division ratio in order to down convert the output signal to fo. 1. LNA The GPS signal that passes through the antenna is input to Pin 27 via a matching circuit as shown in the figure below. The input signal is amplified by the LNA, and then output from Pin 30. Always use matching circuits for the LNA input pin (Pin 27) and the LNA output pin (Pin 30), and match at 1.57542GHz. 2. RF Amplifier, RF Mixer, IF Phase Shifter and Adder The signal amplified by the LNA passes through the SAW filter, and is then input to Pin 34 via a matching circuit. The input signal is amplified by the RF amplifier, and then down-converted by the RF mixer to the fo (1.023MHz) I and Q components. The IF signal down-converted to the I and Q components has the image component eliminated by the phase shifter and the adder, and is then input to the IF filter. Always use a matching circuit for the RF amplifier input pin (Pin 34), and match at 1.57542GHz. Matching Circuit 27 LNA Matching Circuit 30 fo SAW Matching Circuit 34 1540fo Shifter To IF filter Adder 0 90 35 90 fo: 1.023MHz 3. IF Filter The IF signal that passed through the adder has the undesired components outside the band eliminated by the IF Filter. In fo mode the signal passes through only the LPF and is input to IF AMP2. Set the serial data setting register FIL to "0" for fo mode (LPF), otherwise IF output level is extremely low. In addition, an external filter can also be connected to this IC using Pins 40 to 43. From Adder IF Filter To IF AMP2 - 16 - CXA3355TQ 4. IF AMP2 and A/D Converter The signal that passed through the IF filter is amplified by IF AMP2, converted into binary signal by the A/D converter, and then output from the DATA output pin (Pin 8). The A/D converter performs sampling at the TCXO CLK. In addition, the A/D converter output voltage High level is VCC2 (1.6 to 3.3V), so a wide range of interfaces can be supported. 5. TCXO (Pin 15) Input the signal from the external oscillator to Pin 15 via a capacitor as the reference signal. Input frequencies from 10MHz to 26MHz are supported. The input signal level from the external oscillator should be 1.2Vp-p or less (0.6Vp-p typ., 0.2Vp-p min.). This is also the same in power save mode. However, using the typical level of 0.6Vp-p is recommended from the viewpoint of reducing disturbance waves to the receiving system. 6. TCXO CLK Output (Pin 14) This IC can output TCXO CLK from Pin 14 according to the serial data setting. The output voltage High level is VCC2 (1.6 to 3.3V), so a wide range of interface can be supported. Set the serial data setting register CLK to "0" when not using TCXO CLK, or to "1" when using TCXO CLK. (See page 13.) 7. PLL/VCO The PLL is comprised by a VCO, frequency divider and phase/frequency detector, as shown in the figure below, and incorporates an inductor, varactor. The loop filter is externally connected. Use components that satisfy the required characteristics. Serial data setting is unnecessary when this IC is used with the typical TCXO and IF combinations set by the initial settings shown in page 12. This IC becomes unnecessary in the combination of typical TCXO and IF by serial data initial setting. When making serial data settings, set counter frequency division values that satisfy the following equations. * fVCO = (M x N + A) x (fTCXO x 2) / R * (fTCXO x 2) / R > 800kHz * N 3, R 3 fVCO: VCO oscillation frequency, fTCXO: TCXO frequency MC data = N, SC data = A, RC data = R, DMPS data = M = 24 (fixed) To RF phase shifter Frequency division ratio (M x N) + A DMPS VCO 1/M, 1/(M + 1) M = 24 MC 1/N Loop filter SC PFD 1/A CP 18 VCC1 RC x2 1/R 15 TCXO (10MHz to 26MHz) 8. ENABLE (Pin 48) Active mode and power save mode can be switched according to the level. * High (V_IH: 1.2V min.): Active mode * Low (V_IH: 0.2V max.): Power save mode - 17 - CXA3355TQ Application Circuit SAW Filter VCC1 VCC1 VCC1 VCC1 VCC2 (LNA) (RF) (IF) (PLL) (IF) 3.3p VCC1 (LNA) 100p 1p 10n 3p 3.9n 4.7p 3.9n 6p 34 RF_INN 33 GND 32 VCC1 (LNA) 31 VCC1 (LNA) 30 LNA_OUT 29 GND 28 GND 27 LNA_IN 26 GND (LNA) 25 GND (LNA) 1 0.1 VCC = 1.8V 3.3p 12p 36 GND (RF) 35 RF_INP 10p VCC1 (RF) 37 GND (RF) 24 GND (LNA) NC 23 38 VCC1 (RF) 39 VCC1 (RF) NC 22 0.1 40 TESTINP VCO_I 21 0.1 41 TESTINN 10n 10n 42 TESTOUTP C_VCO 20 GND 19 24k 100p LPF 18 8p VCC1 (PLL) 17 VCC1 (PLL) 10p VCC1 (PLL) 43 TESTOUTN VCC1 (IF) 1n 44 VCC1 (IF) 45 GND (IF) GND (PLL) 16 10n TCXO input level: 0.2 to 1.2Vp-p 46 NC 33k 47 R_EXT1 VCC2 (IF) DATA_OUT TCXO 15 CLK_OUT 14 VCC2 (IF) R_EXT2 C_EXT 48 ENABLE GND (IF) LT 13 DATA CLK GND NC NC NC NC 1 39k ENABLE pin Vcc2 (IF): Active mode GND: Power save mode 2 3 4 5 6 18n 7 8 9 10 11 12 DATA_OUT 1n VCC2 (IF) Number of parts * Resistors: 3pcs * Capacitors: 20pcs * Inductors: 5pcs * SAW filter: 1pc Note) 1. This diagram shows the application circuit when the initial settings are made for 4fo mode. (See page 13.) 2. The RF block bypass capacitors should have excellent high frequency characteristics. 3. Use parts with a tolerance of 1% for the following resistor elements. Other parts should have a tolerance of 5%. * Pin 1 (R_EXT2) * Pin 18 (LPF) * Pin 47 (R_EXT1) Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. - 18 - CXA3355TQ Supplement Materials (Example of representative characteristics) Graph 1. ICC 20 10 5 IF AMP2 output level [dBm] 0 -5 -10 -15 -20 -25 -30 -35 5 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 Vcc [V] Graph 2. Total Gain 15 Icc [mA] 10 fo VCC1 = VCC2 = 1.8V Temp = 25C -40 -135 -130 -125 -120 -115 -110 -105 -100 -95 -90 -85 LNA_IN input level [dBm] Graph 3. Total NF 10 -20 -25 8 -30 -35 Total NF [dB] fo mode IMRR [dBc] 6 -40 -45 -50 -55 -60 0 0 1 2 3 4 5 Frequency [MHz] -65 0.1 Graph 4. Image Rejection Ratio VCC1 = VCC2 = 1.8V Temp = 25C 4 VCC1 = VCC2 = 1.8V Temp = 25C 2 1 Frequency [MHz] 10 Graph 5. Filter Response (Normalized at 1.023MHz) 10 5 0 Filter response [dB] -5 -10 -15 -20 -25 -30 -35 0.1 1 10 100 VCC1 = VCC2 = 1.8V Temp = 25C fo Upper spec (fo) Lower spec (fo) Frequency [MHz] - 19 - CXA3355TQ Graph 6. Local Leak -60 VCC1 = VCC2 = 1.8V Temp = 25C -65 Local leak [dBm] -40 Graph 7. C/N VCC1 = VCC2 = 1.8V Temp = 25C -50 -70 C/N [dBc/Hz] -60 -70 -75 -80 -80 -90 -85 LNA_IN of EVB -100 0.01 0.1 1 Frequency difference from the carrier [MHz] - 20 - CXA3355TQ Package Outline (Unit: mm) 48PIN TQFP (PLASTIC) 9.0 7.0 1.2MAX B 36 37 A 25 24 A 48 1 0.5 0.2 0.03 X4 0.2 0.25 0.1 0.05 0.2 0.03 S AB 12 13 X4 0.2 S AB B (8.0) 0.1 (0.5) S 0.08 S AB S DETAIL B:PALLADIUM 0 to 8 0.6 0.15 (0.5) DETAIL A SONY CODE EIAJ CODE JEDEC CODE TQFP-48P-L01 P-TQFP48-7.0X7.0-0.5 PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.2g - 21 - 0.125 0.02 Sony Corporation |
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